1. Field of the Invention
This invention relates to semiconductor package structure, and more particularly to a semiconductor package structure having universal lead frame and heat sink.
2. Description of Related Art
In the semiconductor industry, the semiconductor packaging, being the last stage of manufacturing process of integrated circuit products, is used for providing a medium of electrical connection between a chip and a printed circuit board (PCB) or other appropriate devices and is also used to protect the chip. Generally, the integrated circuit is encapsulated in a package, then the package is bonded to the printed circuit board or a substrate.
It is the demand of the market makes the semiconductor industry grow very fast, and the level of integration of integrated circuit is getting higher than ever. Consequently, the number of input/output port is increasing, and the package is heading for developing the one with high density. Therefore, the design and fabrication of a die pad used for mounting the chip while performing packaging, and of a printed circuit board or a substrate such as a circuit carrier for the connection of electronic parts needs to be improved. As the speed of calculating process is getting higher and higher, the power consumed and the heat generated is also getting higher and higher. The heat generated after the chip is packaged is not easy to spread away. The conventional way of heat dissipation is to let the heat dissipate by means of the heat conduction through the molding compound, but the molding compound universally used is not a good thermally conductive material. For all of the above-mentioned reasons, the heat-dissipating effect of heat dissipation method provided by the conventional package is very limited.
FIG. 1A is a cross-sectional view of a semiconductor package according to the prior art. As shown in FIG. 1A, a semiconductor package is constructed on a leaf frame 106. The package comprises a die pad 102 having a top surface 104, and a plurality of leads 108. The leads 108 are attached on the top surface 104 and are disposed at the periphery of the die pad 102. A chip 100a mounted on the top surface 104 of the die pad 102 is electrically connected to the leads 108 by bonding wires 110a.
As the manufacturing technology of the semiconductor has advanced to 0.18 Micron of wire width or even smaller, there are a lot of breakthrough on increasing the integration. Accordingly, the chip size is diminished, and the electronic products are in the trend of "Light, Thin, Short, and Small". However, as the chip is shrunk, under the same condition of using the same lead frame, the distance between the chip and the leads of the lead frame will be increased.
Similar to FIG. 1A, shown in FIG. 1B is a schematic cross-sectional view of the semiconductor according to the prior art when the chip is shrunk. As shown in FIG. 1B, a chip 100b mounted on the top surface 104 of the die pad 102 is electrically connected to the leads 108 by bonding wires 110b. As compare with the package shown in FIG. 1A, when the chip is shrunk from 100a to 100b while all the other elements of the package keep the same size and same disposition, the required bonding wires become longer from 100a to 100b. This is due to the fact that the space between the chip 100b and the leads 108 in FIG. 1B is larger than the space between the chip 100a and the leads 108 in FIG. 1A. The length increase of bonding wires not only increases the manufacturing cost but also affects the electrical performance of the package. Moreover, the encapsulating process can cause the "Wire Sweep" or even the "Wire Cross" of the relatively long bonding wire that results in unnecessary "Short Circuit".
However, one way to keep the length of the bonding wires unchanged when the chip is shrunk from 100a to 100b is to make the leads approach toward the center of the lead frame, in other word, to make the leads relatively longer. Accordingly, the lead frame needs to be redesigned and remanufactured which will result in the increase in manufacturing cost too. In other word, the original lead frame can not be used when the size of the chip is changed (either shrunk or enlarged).